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SN74HC174NSR

2V~6V 50MHz D-Type Flip Flop DUAL 74HC174 16 Pins 8μA 74HC Series 16-SOIC (0.209, 5.30mm Width)

Manufacturer: Texas Instruments
Origchip NO: 815-SN74HC174NSR
Package: 16-SOIC (0.209, 5.30mm Width)
Datasheet: PDF
Stock: 977
Description: 2V~6V 50MHz D-Type Flip Flop DUAL 74HC174 16 Pins 8μA 74HC Series 16-SOIC (0.209, 5.30mm Width)(Kg)

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Details

Tags

Parameters
Terminal Form	GULL WING
Peak Reflow Temperature (Cel)	260
Supply Voltage	5V
Base Part Number	74HC174
Function	Master Reset
Output Type	Non-Inverted
Operating Supply Voltage	5V
Number of Elements	1
Polarity	Non-Inverting
Supply Voltage-Max (Vsup)	6V
Supply Voltage-Min (Vsup)	2V
Number of Circuits	7
Load Capacitance	50pF
Output Current	5.2mA
Clock Frequency	50MHz
Propagation Delay	200 ns
Turn On Delay Time	14 ns
Family	HC/UH
Logic Function	D-Type, Flip-Flop
Current - Quiescent (Iq)	8μA
Current - Output High, Low	5.2mA 5.2mA
Max I(ol)	0.0052 A
Number of Bits per Element	6
Max Propagation Delay @ V, Max CL	27ns @ 6V, 50pF
Prop. Delay@Nom-Sup	40 ns
Trigger Type	Positive Edge
Input Capacitance	3pF
Power Supply Current-Max (ICC)	0.08mA
Number of Input Lines	3
fmax-Min	29 MHz
Clock Edge Trigger Type	Positive Edge
Max Frequency@Nom-Sup	25000000Hz
Height	2mm
Length	10.3mm
Width	5.3mm
Thickness	1.95mm
Radiation Hardening	No
RoHS Status	ROHS3 Compliant
Lead Free	Lead Free
Factory Lead Time	6 Weeks
Lifecycle Status	ACTIVE (Last Updated: 3 days ago)
Mount	Surface Mount
Mounting Type	Surface Mount
Package / Case	16-SOIC (0.209, 5.30mm Width)
Number of Pins	16
Weight	200.686274mg
Operating Temperature	-40°C~85°C TA
Packaging	Cut Tape (CT)
Series	74HC
JESD-609 Code	e4
Pbfree Code	yes
Part Status	Active
Moisture Sensitivity Level (MSL)	1 (Unlimited)
Number of Terminations	16
ECCN Code	EAR99
Type	D-Type
Terminal Finish	Nickel/Palladium/Gold (Ni/Pd/Au)
Subcategory	FF/Latches
Packing Method	TR
Technology	CMOS
Voltage - Supply	2V~6V
Terminal Position	DUAL

SN74HC174NSR Overview

The flip flop is packaged in 16-SOIC (0.209, 5.30mm Width). Package Cut Tape (CT)embeds it. It is configured with Non-Invertedas an output. It is configured with the trigger Positive Edge. In this case, the electronic component is mounted in the way of Surface Mount. The JK flip flop operates with an input voltage of 2V~6V volts. It is operating at a temperature of -40°C~85°C TA. The type of this D latch is D-Type. This type of FPGA is a part of the 74HC series. In order for it to function properly, its output frequency should not exceed 50MHz. The list contains 1 elements. This process consumes 8μA quiescents. 16terminations have occurred. This D latch belongs to the family of 74HC174. The power source is powered by 5V. A JK flip flop with a 3pFfarad input capacitance is used here. This D flip flop belongs to the family of HC/UH. It is mounted in the way of Surface Mount. Basically, it is designed with a set of 16 pins. The clock edge trigger type for this device is Positive Edge. This device has the base part number FF/Latches. It reaches 6Vwhen the supply voltage is maximal (Vsup). If you want to maintain normal operation, you should keep the supply voltage (Vsup) above 2V. To achieve this superior flexibility, 7 circuits are used. In view of its reliability, this D flip flop is a good fit for TR. For high efficiency, the supply voltage should be set to 5V. The 5.2mA output current allows it to be designed with the greatest amount of flexibility. The number of input lines is 3.